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Design Techniques to Reduce Power Consumption

Authored on: Feb 6, 2006 by Arthur Yang

Technical Paper

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Each generation of FPGAs gets increasingly faster, denser, and larger. What can you do to ensure that power doesn't increase in conjunction? A number of design decisions can impact the power consumption of your system, ranging from the obvious choice of device selection to the more minute details of choosing state machine values based on frequency of use.

To understand why the design techniques we'll discuss in this article conserve power, let's give a brief primer on power consumption.

Reprinted with permission from Xcell Journal / Third Quarter 2005. Article © Xcell Journal.

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