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Efficient DSP Algorithm Development for FPGA and ASIC Technologies

Authored on: Aug 14, 2007 by Shiv Balakrishnan and Chris Eddington

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This white paper discusses the challenges and requirements of creating portable algorithmic IP for field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). It illustrates how an ESL synthesis methodology using Synplicity's Synplify digital signal processing (DSP) tool — which automatically creates optimized and synthesizable real-time logic (RTL) implementations — can significantly reduce the time and effort required to implement either technology. An example of a basic DSP building block, a 65-tap FIR filter, is used to describe the process for implementation-aware logic synthesis and design exploration.

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