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Design Trends for High-Speed, Low-Power Connectivity IP at the Physical Layer

Authored on: Apr 2, 2009 by Navraj Nandra

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Low power and high speed have typically been poles apart in terms of product and semiconductor technology features—traditional engineering wisdom indicates that one feature cannot not be achieved without compromising the demands of the other. The rules, however, are changing. This article will describe the design trends and implementation challenges faced when trying to achieve both high speed and low power from the physical-layer (PHY) perspective.

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