Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies
The physical layer is responsible for the transmission of the raw bit stream over the PHYsical transport medium and is the lowest layer within the OSI network model. With high-speed interfaces, such as the serial protocols USB 2.0, PCI Express, SATA, and DDR2, the PHY serves as a bridge between the digital and modulated parts of the interface. The trend is to integrate these mixed-signal interfaces into systems-on-a-chip (SoCs) that are manufactured in digital logic deep sub-micron technologies with channel lengths of 65-nm and 45-nm. These technologies are tuned for digital integration and pose a number of challenges to the mixed-signal circuit designer, such as low operating voltages that reduce head room for analog circuits.
After an introduction to circuit and process trends in deep sub-micron technologies, this paper presents a complete protocol solution using the high speed memory DDR2 interface as an example. This is followed by a description of the implementation challenges of integrating intellectual property (IP) into a system-on-a-chip (SoC). The paper concludes with a proposal for production testing a high-speed serial PHYs.