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Infusing Speed and Visibility into ASIC Verification

Authored on: Jan 5, 2007 by Mario Larouche

Technical Paper

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High-performance, high-capacity FPGAs continue to experience an exponential growth in usage, both in their role as prototypes for ASIC/SoC designs and as systems in their own right. These designs typically involve complex combinations of hardware and embedded software (and also, possibly, application software). This is resulting in a verification crisis, because detecting, isolating, debugging, and correcting bugs now consumes significantly more time, money, and engineering resources than creating the design in the first place.

This paper first provides an overview of the various conventional verification options available to designers and summarizes the advantages and disadvantages of these different techniques. The paper next introduces an innovative, patented new technology called TotalRecall, which provides 100% visibility into an FPGA—including the registers, combinational logic, and memory blocks—while allowing the FPGA to be used at full real-time.

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