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A Reference Verification Methodology for Vera

Authored on: Nov 16, 2004

Technical Paper

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Verification is one of the single biggest challenges in the design of system-on-chip (SoC) devices and reusable IP blocks. Complex blocks, especially when integrated together, represent huge state spaces that are difficult to exercise under all the possible conditions that will be encountered in the real application of the chip once deployed. Anticipating all possible corner cases and discovering deeply buried design bugs is one of the key verification challenges. Given the realities of project resources and time-to-market demands, it is also critical to find these bugs as early in the process as possible and with as little effort as possible.

The best way to address this problem is to take full advantage of available verification tools and techniques by using a unified and comprehensive methodology. This article outlines just such a solution: a reference verification methodology for the Vera testbench automation solution. This methodology makes the coverage driven, constrained-random techniques used by experts available to any SoC or IP development team.

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