Attacking the Verification Challenges: Applying Next Generation Verification IP to Bus Protocol-based Designs
This paper illustrates the challenges facing design and verification engineers developing next generation products and systems. Increasing design size and complexity are forcing a transformation of verification methodologies to adequately test new products. This transformation is to higher levels of abstraction in testbench languages and verification IP, enabling the creation of smarter testbenches. It is being led by verification models that have capability beyond traditional bus functional models and can be used with a variety of testbench languages. Models also vastly reduce the time-to-first-test within a high-level testbench.