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Unique Graph-Based Physical Synthesis Technology: For Fast Timing Closure and Improved Performance of FPGA Designs

Authored on: Nov 30, 2005 by Chris Eddington

Technical Paper / Product Paper

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Traditional synthesis technology is failing to address the needs of today's extremely large and complex FPGA designs implemented in devices at the 90 nm technology node and below. The problem is that conventional FPGA synthesis engines are based on ASIC-derived techniques such as floorplanning, in-place optimization (IPO), and—more recently—physically aware synthesis. However, these ASIC-derived synthesis algorithms are not appropriate for use with the regular architectures and pre-defined routing resources presented by FPGAs.

The end result is that all three of the traditional FPGA synthesis approaches require multiple time-consuming iterations between front-end synthesis and downstream place-and-route tools so as to achieve convergence and timing closure. The solution is a unique graph-based physical synthesis technology that provides a single-pass, push-button synthesis step requiring zero (or very few) iterations with the downstream place-and-route engines. Furthermore, graph-based physical synthesis can provide 5 to 20% performance improvement in terms of the overall clock speed of the system. The first product to feature graph-based physical synthesis technology is Synplify Premier advanced FPGA physical synthesis, which is tailored for high-end FPGA designers whose designs are of a complexity that mandates a true physical synthesis solution.

This paper first presents the main conventional synthesis approaches and explains the problems associated with these techniques. The paper then introduces the concepts underlying graph-based physical synthesis and shows how this technology uniquely addresses the requirements of today's state-of-the-art FPGA architectures.

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