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SystemC and SystemVerilog for Electronic System-Level (ESL) Design

Authored on: Jun 25, 2007 by Rindert Schutten et al

Technical Paper / Conference Paper

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In this paper, we take a practical, real-world view to perform the hardware and software aspects of embedded system design, with a solution based on two existing, standard languages—SystemC and SystemVerilog. We explain how with SystemC, abstract, transaction-level models of the design are created and serve as an execution platforms for pre-silicon software development. We outline how these transaction-level models are used as a reference for the hardware implementation, and describe how SystemVerilog's verification capabilities are used to ensure that the software and hardware models are mutually consistent, and that the combined hardware software system meets its specifications.

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