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Creating Performance and Power-Efficient Algorithms for C-to-RTL: Application Engine Synthesis

Authored on: Apr 27, 2006 by Craig Gleason

Technical Paper / Conference Paper

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Compute-intensive algorithms executed in system-on-chip (SoC) devices are increasingly implemented in dedicated hardware engines that operate at higher throughput and with lower power consumption than is generally possible with programmable approaches. This paper discusses the challenges of designing such engines—known as application engines—and describes a proven C-to-RTL synthesis and verification solution, Application Engine Synthesis (AES), that automates the most time-consuming parts of the design. The application of AES to the design of a video coder/decoder is used to demonstrate the efficacy of the solution. The paper concludes with data that demonstrates that the performance and area of AES-designed RTL is comparable to that of manually coded RTL.

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