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Early Hardware/Software Integration Using SystemC 2.0

Authored on: Nov 17, 2006 by Jon Connell and Bruce Johnson

Technical Paper / Conference Paper

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Capabilities added to SystemC 2.0 provide the needed expressiveness and abstraction to model processorbased systems. By representing the system at a transaction-based level, the hardware and software teams share a common abstraction and verification environment. Models of microprocessors are a natural addition to a system modeled at the transaction level. Hardware-software interactions are first defined as processor independent transactions. This view is then refined by adding a processor model which enables the verification of the hardware-software interactions from a very abstract, purely transactional basis, all the way down to the level of verifying the interaction of the software, processor, RTOS, and hardware subsystems.

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