Mobile and high-performance devices require progressively wider I/O interfaces to meet increasing data transfer requirements. These high-speed interfaces are designed using advanced process nodes that are expected to perform within tight timing margins while operating at close to 1V supply voltages. Reliable and predictable chip-to-chip signal transmission depends on the quality of the supply and ground voltage delivered to the I/O circuit and the extent of signal-to-signal and signal-to-power coupling. Traditional approaches of IO/DDR interface validation included Spice based simulation of a small set of bits with some package/PCB parameters.

Sentinel-SSO is a simulation platform for I/O-DDR analysis and optimization. It delivers comprehensive and accurate validation of high-speed parallel I/O interfaces by simulating the complete I/O bank together with the entire power distribution network for on-die, package, and PCB to predict the effect of simultaneous switching noise (SSN) on signal transmission. This presentation will outline the underlying technologies behind Sentinel-SSO and discuss how it provides sign-off accurate I/O-SSO verification with the capacity to handle an entire I/O bank along with package and PCB parasitics.