The Cortex A8 32bit RISC processor based on the ARM core version 7. It
supports a standard 32-bit instruction set and the Thumb2 instruction
set. Thumb2 is a mixed 16 and 32 bit instruction set which provides
better code density while maintaining 32bit-like performance. The Cortex
A8 has a 13-stage execution pipeline and supports dual fetch, dual
issue inline execution. It has 2 levels of cache. Level 1 consists of 16
kB of Instruction Cache and 16kB of data cache; both level 1
instruction and data cache are 4-way set associative caches. Level 2 has
256 kB of unified cache which is 8-way set associative. Join this
session to learn more about TI’s Cortex A8 offering.