Double Data Rate memories DDRx have become new standards in
today’s memory applications. This course describes fundamentals of DDR2 and DDR3 from a signal Integrity perspective. The main signal groups and their synchronism requirements are identified. Net topologies, trace impedances
and terminations play an important role in waveform integrity. Trace length, vias and cross talk play an important role in timing. The effect of these parameters is explained. In the course of a design, one would place constraints and
carry out PCB routing. However, post-route verification can become a tedious task. The Hyperlynx DDRx Batch mode capability combines a comprehensive signal integrity analysis with timing analysis. Its usage to optimize and validate a
DDRx implementation is presented.