Today’s highest performance System on Chip (SoC) contains a growing number of processor cores that need to support simultaneous applications and a wide range of traffic profiles. Many tasks are real-time in nature, meaning that data delivery has to be guaranteed in order to prevent degradation in function or utility. This design challenge has led to significant advancements in on-chip network methodologies over the last decade. In this fundamentals course, we review the major changes in system-level and SoC design leading up to this point, the ways in which these design challenges can be analyzed, how to build the most optimized and scalable SoCs, as well as the critical success factors for increasing bandwidth and achieving peak performance, power-aware and cost-efficient designs.

Several essential solutions are discussed, such as various memory architectures and the most innovative Network on Chip (NoC) topologies. Specifically, we examine how non-blocking networks using virtual channels can ease many of the system problems and provide optimal performance with minimum area for the processor to memory connection.