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There are two main reasons why a designer would need to migrate from an FPGA to an ASIC— and many more reasons why that migration could easily go astray. Regardless of whether the designer intends to deploy first with a low-volume FPGA implementation and then move to an ASIC as volume ramps up, or instead if the FPGA was simply intended to prototype an ASIC to check functionality and perform at-speed verification, there are a number of fundamental principles that designers needs to keep in mind.

This course presents those principles and the tools available to act upon them. It starts by summarizing the main differences between FPGAs and ASICs, moves on to discuss the main issues associated with migrating a design between implementation domains, from RTL, synthesis and timing constraints, to test planning, architecture, packaging, pin-outs and interfaces. Finally we consider a number of target ASIC technologies, including standard cell, structured ASICs and conclude with a real-world example using Altera’s HardCopy ASICs.