Fundamentals of Accelerated Functional Verification
Verification consumes a large part of the total time and budget for complex chip development and is increasing. Verification teams are looking for ways in which the efficiency and effectiveness of their verification efforts can be maximized and in this fundamentals course, we will be looking at two such techniques. The first is the use of abstraction which can hide unnecessary details. Specifically we will look at transaction-level modeling. These models are faster to write, execute much faster than low level models, and they are easier to debug. These models can be used in either the design or the testbench. The second technique is the use of hardware-assisted execution of the design. We will explore the types of hardware-assistance that are available, and the ways in which they can be used. When these two techniques are coupled together they can bring about orders of magnitude performance increases that not only enable more verification to be performed but also enable tests to be executed that could never be attempted with more traditional verification techniques. We will explore the implication that this has on the way that transactor models are created and demonstrate the power that this solution has by booting and debugging an application running on Linux on an implementation model of a processor.
About the Presenter:
Brian Bailey is an independent consultant and freelance writer working in the areas of functional verification and ESL.
Prior to this he was the Chief Technologist for verification at Mentor Graphics.
Bailey has four patents to his name and has published six books on these subjects including:
- ESL Design and Verification
- ESL Models and their Application
- TLM-driven Design and Verification Methodology
He chairs the Accellera ITC standards committee and is on the technical
program committee for several international conferences. He also blogs regularly on EETimes’ ProgrammableLogicDesignline as well as Techbites.com.