Low power architecture means high power efficiency for static consumption in standby mode as well as dynamic consumption in running mode. This class propses a new architecture based on a single SoC that includes a power switching mechanism, a dynamic management of analog cells (sampling mode), and a lower voltage operation. In addition, this new architecture integrates an optimized digital scheme for data transfer, saving clock cycles and reducing the operating frequency, and a high level of system integration, avoiding leakages with external components.