While the PCI Express (PCIe) interconnect standard ” both the original PCIe 1.x and the newer PCIe 2.0 (Gen 2) ” permeates embedded-systems hardware, packet latency continues to impact systems’ overall performance. Latency is the delay between the start and completion of a system’s action, and its greatest impact is in its affect on higher-level functional throughput. When a data packet is forwarded through a PCIe switch, for example, throughput is assumed to be at optimum speeds. This isn’t guaranteed, however, because switch latency varies. But system designers don’t have to resign themselves to latency running amok. This class looks critically and deeply at PCIe packet latency, and provides attendees a greater understanding of how to contend with this issue.