This class focuses on techniques to assign pins for FPGAs to design FPGA boards successfully. First, the different dimensions of the pin selection problem are presented. Next, the problem is abstracted to a higher level. This class shows how this problem can be modelled using graph theory. Presenting a unique approach where the optimal pin selection is achieved through minimization of a graph. With this approach FPGA pins are selected such that they not only meet the FPGA IO DRCs and the logical requirement for the protocol, but are also optimized to minimize the PC board layers.