Engineers new to VHDL-based FPGA design often struggle converting design requirements into a successful FPGA design. The design methodology presented shows FPGA designers how to produce an RTL-level logic design that is easily and quickly converted to VHDL code, simulated, and implemented in the target FPGA. The design process also provides documentation that simplifies FPGA simulation and test. An example design is first presented to demonstrate the process followed by a class exercise.