This session will address the need for critical area analysis (CAA) in the design process. You will learn how Calibre Yield Analyzer supports several flows and capabilities that allow designers to get the details they need to create DFM-aware designs and enforce best practices across multiple design groups and IP providers.

At 45nm and beyond, foundries have made some DFM checks mandatory. Whether you are fabless, fab-lite, or IDM, the goal of reducing a design’s sensitivity to manufacturing issues should ideally be handled by the design teams. The farther downstream a design goes, the less likely a manufacturing problem can be addressed without costly redesign. By addressing DFM problems early, when the design is still in progress, manufacturing ramp-up issues can be avoided.

What You Will Learn

  • General theory and justification for CAA
  • Meaning of Defect Limited Yield (DLY)
  • Use CAA in a library & block/chip flow
  • Perform a memory redundancy analysis
  • Use RVE and DesignRev for batch reporting & design exploration

Who Should View

  • Design Verification Engineers and Managers who want to own their DFM issues
  • Operations/Product Engineers and Managers

Simon Favre

Simon is the Technical Marketing Engineer for Calibre YieldAnalyzer and has a background in Processing, Custom Design, ASIC Design, and EDA. Most recently, he was at Ponte Solutions, which was acquired by Mentor Graphics in May 2008. Simon has an extensive technical knowledge in DFM and has worked with Foundries, IDMs and Fabless semiconductor companies worldwide to find the real value of DFM and to integrate DFM into their design flows.