Join Mentor Graphics for this On-Demand Seminar and Product Demonstration
(held live in San Jose, CA. Dec 2011) and learn how to improve design quality
and mitigate otherwise difficult to find errors within your design and
verification flows with Calibre® PERC™.

Protecting against ESD, Latch-up, reliability and other EOS events can be
challenging, particularly when multiple power domains and thinoxide gates are
used extensively. Detailed SPICE/Mixed-Mode simulation is an often used, but
costly (in terms of runtime, coverage and expertise) step in understanding the
protection your design will enjoy while identifying any potential reliability

During this seminar, we will review how Calibre PERC offers an effective and
easy to use solution that is able to look at the entire design in context and
answer these reliability questions for you, without the need for full

What you will Learn

  • How to detect sources of reliability issues within your designs

  • Benefits of voltage dependant, and voltage aware checks – both on the
    topological representation of your design (netlist), and the physical

  • How to effectively verify signal paths in multi-power domain

Who Should View

  • IC and system design engineers, verification specialists and

Presenter Bios

Dhaval Shah
Dhaval Shah is the Calibre PERC Lead for North Americas
Technical Sales team at Mentor Graphics. He has worked as Application Engineer
supporting Calibre and Analog/Mixed-signal products lines and has over 8 years
of design and field experience. Dhaval holds a B.E. in electronics and
communications and M.S. in electrical engineering from University of Southern

Matthew Hogan
Matthew Hogan is a Calibre Marketing Engineer for
Mentor Graphics. With over 15 years of design and field experience, he is
well-versed in the issues that are imposed on today’s aggressive designs.
Matthew is an IEEE Senior Member and ACM Member. He also holds a B.Eng and an