Presented by Cheryl Ajluni, Sponsored and Developed by Cadence Design Systems, Inc.


The creation of lower power designs continues to be major concern of modern engineering. Through the years, various system and circuit design techniques have been developed to achieve this goal (e.g., better power management, use of advanced materials and both basic and advanced design techniques). Unfortunately, these myriad techniques offer just a patchwork solution that often doesn’t reduce power in places where it will count the most or doesn’t produce the expected power reduction at all. Additionally, such techniques can result in yield loss or even functional failure.

Power-aware design offers a means of overcoming these challenges by allowing the engineer to integrate appropriate power-saving techniques at every stage of the design. While it is challenging and can be risky, it is unavoidable. Without aggressive optimization, power budgets will be missed. Moreover, avoiding advanced techniques will lead to sub-optimal power/performance implementation.

This course will introduce an advanced methodology for achieving power closure in power-aware design. This cohesive specification to GDSII methodology communicates power-related design intent across the design flow, enabling design teams to efficiently produce lower-power electronics. Examples of which design tools to use throughout the flow and how to use them will also be provided.

Intended Audience

This course is intended for designers and engineers looking for an advanced methodology for achieving power closure in power-aware design. Attendees should have a basic understanding of low-power design theory and the various techniques that are currently used to minimize power consumption.