A new approach to 2.5D package reliability will be discussed and results from a GUC HBM2E 3.2Gbps PHY and CoWoS will be presented.

You’ll Learn:

• About HBM I/O and CoWoS bump quality monitoring in GUC’s 7nm and 5nm HBM2E PHYs

• How accuracy was validated in GUC’s 7nm and 5nm HBM2E testchips

• How to monitor quality in the field during normal chip operation

• How to prevent system operation failure and extend chip lifetime

• How to identify marginal IOs and CoWoS bumps via advanced analytics, long before HBM interface failure occurs

• How repair algorithms replace marginal IOs/ bumps with redundant ones at next boot cycle