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Thread: Comments for: "EDA pundits envision more 'ASIC-like tools' for FPGAs"

 
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Permlink Replies: 1 - Pages: 1 - Last Post: Nov 5, 2009 12:29 PM Last Post By: pitchMonk1 Threads: [ Previous | Next ]
pitchMonk1

Posts: 4
Registered: 11/19/08
Comments for: "EDA pundits envision more 'ASIC-like tools' for FPGAs"
Posted: Nov 5, 2009 12:29 PM
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Read the article here: EDA pundits envision more 'ASIC-like tools' for FPGAs
pitchMonk1

Posts: 4
Registered: 11/19/08
Re: Comments for: "EDA pundits envision more 'ASIC-like tools' for FPGAs"
Posted: Nov 5, 2009 12:29 PM   in response to: pitchMonk1 in response to: pitchMonk1
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FPGAs seldom use static power islands.This is because the mapping functions become extremely complex to deal with islands. FPGAs need innovative techniques to lower power. Altera uses Vt scaling which can reduce leakage. In order to lower active power (that too significantly), you need sophisticated techniques. I recently helped an FPGA company to solve the power issue with some innovative techniques. If anyone is interested in knowing more, please leave your e-mail address and I can contact you. Thanks.
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