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EDA Toolsets for RF Design and Modeling
Technical Paper
2 comments
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EDA360: The Way Forward for Electronic Design
Technical Paper
0 comments
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FPGA-Adaptive Software Debug and Performance Analysis
Technical Paper
0 comments
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Fundamentals of Virtual Prototypes for Embedded System Development
Course
1 comments
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20nm Design--How this Advanced Technology Will Transform SoCs and EDA
Technical Paper
0 comments
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Clock and Reset Ubiquity: A CDC Verification Perspective
Technical Paper
0 comments
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Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms
Technical Paper
0 comments
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LPC800: Enhance your 8-bit application with 32-bit possibilities
Webinar
0 comments
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Advanced Motor Control: MCU Considerations
Webinar
0 comments
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Addressing the Complexity of "Smart" Devices Through Low Power Hierarchical Design
Technical Paper
0 comments
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Implementing Efficient Low-Power PCIe Interfaces with Low-Cost FPGAs
Technical Paper
1 comments
EDA | IP
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Subtopics
- Design for Manufacturing (25)
- Design for Test (33)
- IC Design Tools (34)
- Models/Libraries (13)
- PC Board Design (23)
- Place and Route (12)
- Simulation (21)
- Synthesis (14)
- System Design Tools/Methodologies (38)
- Verification (374)
Industry
- Automotive/Transportation (19)
- Communications and Networking Systems or Equipment (7)
- Computers and Peripherals (8)
- Consumer Electronics & Appliances (15)
- Aerospace/Defense/Government (5)
- Industrial/Robotics/Motor Control (14)
- Electronic Instrumentation or Test (9)
- Medical Devices & Systems (12)
- Semiconductor Design & Manufacturing (18)
- Security (4)
Date Range
Closing the Chip Architecture Implementation Feedback Loop
Technical Paper
Posted on: Aug 6, 2009
0 likes
Comparison of Eye Patterns Generated By Synopsys HSPICE and the Agilent PLTS
Technical Paper
Posted on: Nov 16, 2005
0 likes
ESL Technology Backgrounder
Technical Paper
Posted on: May 11, 2005
0 likes
Using the CoolRunner XPLA3 Timing Model
Technical Paper
Posted on: May 25, 2005
0 likes
Maximizing Team Productivity through Efficient Design Data Management
Technical Paper
Posted on: Nov 7, 2006
0 likes
Path Tracing: An Intelligent Verification Technology for Simulation-Based Environments
Technical Paper
Posted on: May 23, 2008
0 likes
Ensuring Correctness Where It Matters Most
Technical Paper
Posted on: Sep 5, 2008
0 likes
Adaptability Breeds Success in IP Development
Technical Paper
Posted on: Feb 23, 2010
0 likes
Automated timing and congestion aware decap Placement for dynamic IR hotspot removal
Technical Paper
Posted on: Sep 29, 2009
0 likes
Modeling Total Cost of Ownership for Semiconductor IP
Technical Paper
Posted on: Jan 25, 2005
0 likes
Discovery AMS Full-Chip Verification of Mixed-Signal Designs
Technical Paper
Posted on: Oct 5, 2004
0 likes
Analog Test Bus Enhances Mixed-Signal Debug and Characterization
Technical Paper
Posted on: Mar 11, 2005
0 likes
Comparison of Wideband Channelisation Architectures
Technical Paper
Posted on: Feb 2, 2004
0 likes
Improved time to market through automated software testing
Technical Paper
Posted on: Jul 20, 2011
0 likes
Motivations and Methodology for Nanometer Library Characterization
Technical Paper
Posted on: Aug 26, 2005
0 likes
SPICE Model Validation Report: EQCD (DV to DV) Cable Assembly
Technical Paper / Product Paper
Posted on: Nov 15, 2005
0 likes
Achieve Faster Timing Closure with Graph-Based Physical Synthesis
Technical Paper
Posted on: Jan 31, 2006
0 likes
New impedance measurement solutions & apps using 5 Hz to 3 GHz VNA
Webinar
60 min
Posted on: Feb 10, 2011
0 likes
Achieving Timing Closure with Bluespec SystemVerilog
Technical Paper
Posted on: May 4, 2007
0 likes
Layout and Physical Design Guidelines for Capacitive Sensing
Technical Paper / Application Note
Posted on: Aug 8, 2007
0 likes