With the launch of Intel's P35 chip sets, the growing list of validated devices and AMD's planned support, DDR3 SDRAMs have become a reality.
Intel has validated DDR3 SDRAMs from manufacturers including Elpida, Hynix, Micron, Nanya, Qimonda and Samsung. The compliant devices have densities of 512 Mbits and 1 Gbit, with performance ratings of 800 MHz and 1,066 MHz. Most are manufactured in 90- or 80-nm process nodes. Given the pace of DRAM manufacturers' migration to devices that are 70 nm and smaller--which will make 1-Gbit DDR3 SDRAMs more cost-effective--some industry experts predict the 512-Mbit DDR3 market will become insignificant compared with that for 1 Gbit and higher.
Semiconductor Insights performed comparative analyses on two of the leading 1-Gbit DDR3 SDRAMs, from Samsung and Micron. The devices are manufactured in comparable process nodes--Samsung's in 80-nm lithography and Micron's using 78-nm lithography.
Samsung 1-Gbit, 80-nm DDR3
The Samsung sample has a die size of 127 mm, and the DRAM cell size is 0.053 µm. Bonding pads are located in the center of the chip in two rows. The internal data bus and the related pipeline circuitry supporting the DDR3 8-bit prefetch architecture appear to be placed in the center of the chip vertically. Compared with the Micron 1-Gbit DDR3 SDRAM, the use of two rows of bonding pads appears to allow more signal routing channels between the upper 512-Mbit half and the lower 512-Mbit half.
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A close-up of the Samsung DDR3 shows the internal data bus and related pipeline circuitry centered vertically with the bonding pads in the center of the chip in two rows.
Source: Semiconductor Insights |
Two rows of column decoders appear to be placed in the upper and the lower half of the chip. This reduces the length of column select lines compared with the Micron architecture. Samsung's architecture appears to be designed to achieve high performance by having shorter column select lines and shorter local data bus lines.
Samsung's DRAM cell is an 8F2 cell with a metal-insulator-metal (MIM) capacitor. The DDR3 device uses a spherical recess-access transistor with a gate length of 47 nm. The wordline width and pitch are 47 µm and 165 nm, respectively. The bitline width and pitch are 40 nm and 160 nm.
Micron DDR3
The Micron 1-Gbit DDR3 sample's die size is 102 mm2, and it has 38 percent cell efficiency. Micron's 6F2 cell, with an area of 0.0365 µm2, is the smallest DRAM cell that Semiconductor Insights has analyzed.
It appears that use of copper interconnect for metal 2 and metal 3, combined with smaller cell size, helped Micron designers achieve desired performance with 1-Gbit DDR3 design. Despite there being a long distance for signals to travel in the larger die, relatively low resistivity and a low-profile copper interconnect helped reduce signal resistor-capacitor (RC) delay as well as power consumption.
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A close-up of the Micron DDR3 shows one row of bonding pads horizontally in the center of the die with column decoders, internal data bus, and pipeline control circuitry arranged in the center of the die next to memory arrays.
Source: Semiconductor Insights |
