Multilevel cell (MLC) NAND flash technology creates memory that is more dense and more affordable by allowing each memory cell to store 2 bits of information, effectively doubling capacity. Current generations of MLC flash overcame data reliability, performance and flash management problems that were inherent in early designs and have gained many design wins as a result, especially in mobile handsets and other consumer electronics.
MLC programming poses challenges in terms of both performance and device reliability. Placing four states in a NAND flash cell requires a high-voltage source (roughly 20 V) to trigger Fowler-Nordheim (FN) tunneling. The reading of MLC NAND flash uses various levels of word line voltages to sense different states programmed through the FN tunneling process.
The use of high voltages in MLC NAND flash involves design challenges to control noise generated by the capacitive-coupling effect of internal signals. Floating-gate-to-floating-gate (FG-to-FG) noise causes the cell's threshold voltage to shift by programming its neighbors. Back pattern noise, which is caused by programming other cells in the same NAND string, will degrade cell current. Source line noise and noise coupled to the p-well also degrade performance. Coupling between selected and unselected word lines, and between the selected gate and its neighboring word line, is another challenge.
Manufacturers have employed various design techniques to eliminate or mitigate coupling-noise-induced problems.
Waveform analysis provides the details of the programming algorithm that a manufacturer has used for a particular device. Done by probing various internal signals, such as word lines, bit lines, source lines and p-wells, waveform analysis is a valuable tool from a competitive intelligence perspective, because it shows the various ways that an operation or function can be implemented.
Design methodology for MLC NAND flash control logic can pose difficulties in any circuit analysis. The use of synthesized logic or of automatic placement and routing methodology and the potential use of a microcontroller with on-chip ROM for the control circuit make it difficult to extract and understand the MLC programming/control scheme without the use of waveform analysis.
Semiconductor Insights has analyzed two leading NAND flash manufacturers' latest 8-Gbit MLC devices using state-of-the-art waveform analysis techniques. SI's waveform analyses reveal some of the cell-programming algorithms and make them easier to understand.
Toshiba TC58NVG3D4CTG00
Toshiba's TC58NVG3D4CTG00 is a 3.3-V 8-Gbit MLC NAND flash device manufactured on a 70-nanometer CMOS process. Programming: (States "10," "00" and "01") is accomplished in the device by attracting electrons to the floating gate. The threshold voltage across each memory cell is divided into four levels that are controlled by the amount of electrons on the floating gate. This is accomplished through FN tunneling.
Incremental Step Pulse Programming (ISPP) is implemented to achieve the programming states. A high positive potential in the range of 17 to 25 V is applied to the selected word lines in short incremental pulses with two step sizes, depending on the programming phase.
Unselected word lines are pulsed with a bypass potential or a cutoff voltage, depending on their position in the string relative to the bit line.
The selected bit lines are grounded, while the unselected bit lines are raised to a 3-V potential to inhibit programming. The source line is raised to 2 V to float the source-line side of the string during programming. The high positive electric field will attract electrons in the channel toward the floating gate.
