Standard-cell-based design has become the mainstream methodology for designing the digital-logic sections of ASICs. The approach has allowed designers to scale ASICs from their origins as simple, single-function ICs, consisting of several thousand gates, to today's complex, multimillion gate systems-on-chip.
The use of standard cells allows for design abstraction, whereby a low-level VLSI layout is represented in a high-level hardware description language (HDL). Physical implementation of an HDL description is achieved using a logic synthesis tool, place and route software, and a standard-cell library.
A standard cell is a group of transistor and interconnect structures, having a defined layout, that provides a Boolean logic function or a storage function. A cell library is a collection of standard-cell elements. The simplest standard cells are direct representations of the elemental NAND, NOR and XOR Boolean functions. Cell libraries also consist of cell elements of much greater complexity, such as 2-bit full adders or muxed D-input flip-flops.
The library usually contains multiple implementations of the same logic-function, differing by drive strength and speed, and as a result by area. Typical cell libraries consist of several hundred elements and allow raw gate densities of more than 400k gates/mm2 for a 90-nanometer process. (Raw gate density uses the area of a NAND2 [with normal drive strength] standard cell as equivalent to one gate.)
Normally, the standard-cell elements all have a constant height, which allows the cells to be butted together into rows. Thus the "standard cell" area of the chip will consist of a large number of cells placed in rows with power and ground bused at either the head or the foot of the row. The placement and interconnection between standard cell elements is performed by automated place and route tools and depends on the circuit logic to be implemented.
With the advent of flip-chip and other packaging technologies, die designs are no longer pad limited but core limited. The density of standard cells, hard macros and embedded memories determines the density of core-limited circuit layouts.
Standard-cell libraries may be optimized for density, speed, voltage or leakage. For example, in some SoC designs, power consumption may be a significant factor; hence, a specific standard-cell library may be used for the express purpose of lowering power consumption, even at the expense of speed. Other compromises may have to be made, such as trade-offs between compact cell size and routability or porosity.
Therefore, by comparing the standard-cell libraries used to design integrated circuits, manufacturers can determine the level of sophistication of the cell library and allow device architects to benchmark their devices against the competition.
Semiconductor Insights (SI) enables a device manufacturer to benchmark its design against the competition by using proprietary software, tools and laboratory techniques. For example, SI extracted the standard-cell library used in the Texas Instruments Omap2420 applications processor.
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SI calculated cell utilization for the 2420 by dividing the areas of all functional cells by the total area analyzed.
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