The quest for a universal memory is the stuff of chip industry folklore. In the early days, phase-change RAM (PCRAM), magnetoresistive RAM (MRAM) and ferromagnetic RAM (FRAM) were seen as the three main contenders in the race to replace flash, SRAM and DRAM with a single memory.
Cypress Semiconductor first released its version of MRAM in 2005 but pulled it from the market shortly thereafter, fearing SRAM and DRAM sales would prevent any real market penetration. Several years down the road, a 4-Mbit MRAM is being produced by Freescale, and FRAM use continues to grow in specific niche applications. Currently, however, the industry is focusing on PCRAM.
It appears that PCRAM, with its industry backers, will become the flash replacement of choice. STMicroelectronics, Intel and Ovonyx have been collaborating on phase-change development since 2003. Even considering the ghost of universal memory, there is still a ways to go to meet the endurance levels that would be required for a true SRAM or DRAM replacement.
In the absence of parts to analyze, recently issued U.S. patents and published applications provide a glimpse into the technology. The memory cell of a PCRAM is based on an element of phase-change material (PCM) that is often derived from a family of materials known as chalcogenides.
Many of the recently issued patents in the field center on the materials and structure of the unit cell. This indicates that development work is still focused on the new materials system, while the associated circuitry is likely imported from current memory technologies.
What follows is a brief overview of what Semiconductor Insights believes are interesting patent documents. This should not be construed as a comprehensive review of the PCRAM patent landscape. The selected patents, from Intel, Ovonyx, STMicroelectronics and Samsung, appear to present interesting solutions to technological challenges faced by PCRAM.
Storage mechanism
To put the patents selected for this overview in context, one should consider the basic mechanism of data storage within PCRAM.
Figure 1 presents a generic temperature-vs.-time diagram for a PCM. For the purposes of this discussion, the PCM is considered to be originally in the crystalline phase. To obtain the amorphous phase, the PCM is heated to a temperature above its melting temperature (Tm)--which for many chalcogenides is around 600°C--and rapidly cooled, as illustrated by Curve 1.
(Click on image to enlarge)
For a PCRAM, heating is achieved through the application of a current to the element itself or by a heating element directly adjacent to the PCM element. This current is known as IRESET. With this process, a "0" is written to the memory cell. If a "1" is to be written to the memory cell, the temperature of the PCM must be raised to a temperature above the crystallization temperature (Tc) and held at this temperature to allow for the nucleation and growth of the crystalline structure, as illustrated by Curve 2. In this case, the applied current is known as ISET.
Two problems beset the processes for writing ones and zeros to a memory cell, and much of the current research and many of the issued patents are directed at solving those problems, either directly or indirectly.
First, the current associated with raising the PCM to the required temperature is quite large. In fact, it is large enough to cause concern as to whether a cell access transistor can continue to provide the required current as process geometries decrease.
The scaling ratios were first discussed in a 2003 International Electron Devices Meeting technical paper by Stefan Lai of Intel. The temperatures for the phase change are set by the phase diagram, requiring one to look at a means of increasing the efficiency of heating. This may include increasing the current density, reducing the volume of material that undergoes the transformation and reducing the conductivity of heat away from the heated volume.
Second, the endurance associated with the PCM phase transformation (i.e., between amorphous and crystalline) should be infinite. A volume change is associated with this transformation, however, that creates large stresses within the PCM element. As such, this stress is likely a wear-out mechanism for the cell, since high cycle counts will take their toll on the various interfaces around the PCM element.
There are many variations on the theme of reducing the programming current; however, two common "base" structures have emerged. Samsung generally appears to implement a planar PCM element that sits between a plug of a first diameter and a contact of a second diameter, where the second diameter is larger than the first. This structure is illustrated in USP 7,130,214.
Intel and Ovonyx appear to implement a PCM element that is deposited in a pore that has been etched in one or more dielectric layers. The shape of the PCM element is defined by sidewall spacers that are formed in the pore. This structure is illustrated in, for example, USP 7,183,567. In both cases, the different contact area between the two contacts and the PCM element forces a higher current density at the contact with the lower surface area, thereby promoting a higher current density and lower current for the required heating.
Within the above two base structures lie variations directed at reducing current. In USP 7,130,214, Samsung discloses a method of applying current, with prescribed levels and durations providing more finely dispersed nuclei. It is taught that this method provides for the desired reduction in programming current. Samsung's published U.S. patent application 20060152186 discloses a method whereby the direction of current is reversed from the "traditional" direction such that current flows from the PCM element to the smaller-diameter contact. It is taught that this further concentrates the current, thereby causing a reduction in the current required for programming.
Finally, USP 7,061,013 discloses a PCM element that contains sublayers of high- and low-resistance PCM material.
Two Intel/Ovonyx patents will be highlighted in the theme of current reduction. Ovonyx's USP 7,049,623 discloses a rather interesting cell structure (Figure 2). PCM element 18 follows the common Intel/Ovonyx structure, where it is deposited in pore 46 with sidewall spacers 22. Of note are high- and low-resistance contact layers 24 and 26, respectively. High-resistance layer 24 acts as a heater, while low-resistance layer 26 ensures even current distribution in providing current to layer 24. Further, layers 24 and 26 lie above conductive liner 30 and insulator 28, which fills and surrounds the conductor. This appears to be a unique way of forming contact between the substrate and layer 26.
Claim 1 recites a limitation directed to the presence of layers 24 and 26. A similar cell structure was used for ST's 8-Mbit 0.18-µm demonstrator at the 2004 VLSI Symposium, as well as the newer, 128-Mbit device, and is covered by USP 6,972,430B2, by G. Casagrande et al., which is co-owned by ST and Ovonyx. The cell structure claimed here seems to provide a smaller cell area and associated better management of current levels, thus addressing a key implementation challenge of PCRAM.
Finally, Intel's USP 7,029,978 discloses a pore-type structure. In it, the PCM element is deposited adjacent to a dielectric layer, which is adjacent to the conductor. It is taught that the dielectric can be bombarded by, for example, ion implantation such that the dielectric breaks down in a specified region.
This appears to be a means of concentrating the current flow through a small region of weakened dielectric. In Claim 11, a memory is said to have a breakdown layer between a pair of electrodes, with "said breakdown layer being ion implanted to increase the likelihood that a breakdown will occur in one region. . . ." Neat idea.
Another broad area of interest is the use of a heater element to supply the required heat to the PCM element. Both Samsung and Intel/Ovonyx have patents disclosing such a structure. In particular, USP 7,170,777, assigned to Samsung, discloses a resistive heater that is associated with each unit cell. The disclosed structure has no access transistor, and the heater has separate select circuitry.
Presumably, the circuitry overhead is considered manageable for improvements in density, as there is no access transistor whose size is dictated by driving sufficient current to heat the PCM. While the patent has a priority date of Oct. 28, 2004, it appears to have broadly claimed a heating structure with separate select lines.
The question of endurance seems to be a bit more nebulous, since apparently few people are talking about it. As stated previously, the theoretical endurance of an isolated PCM element is infinite, since it is simply cycling through a phase transformation. Researchers point out, however, that the volume change associated with this process can create large stresses within the PCM and adjacent layers. They further note that a structure of Ti/TiN adhesion layers can create stresses under thermal cycling that mitigate the stresses associated with the PCM.
In USP 7,129,531, Ovonyx discloses a structure of TiN adhesion layers wherein the layer adjacent to the PCM is rich in Ti. It is noted in the specification that it is believed this chemistry promotes adhesion through a reaction between Ti and tellurium of the PCM element. Fatigue and delamination of the boundary layers are promoted by and associated with the volume change of the PCM element.
At Semiconductor Insights, we look forward to getting our first glimpses of the forthcoming phase-change RAM offerings to determine the implemented unit cell structure--and, in the process, to confirm the approaches that have been taken to bring phase-change RAMs to market. n
Paul Boldt (paul.boldt@semiconductor.com) is IPinsights analyst at Semiconductor Insights (Kanata, Ontario). Earlier, he drafted and prosecuted patent applications at one of Canada's largest IP law firms. He received a PhD in materials science in 1998 from Mc-Master University (Hamilton, Ontario).
