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Clive Maxfield
Site Editor, Programmable Logic DesignLine
TechOnline
Good grief Charlie Brown. It seems like we only recently finished celebrating the dawn of this new millennium (who amongst us could forget the "Y2K" moniker?), and now Christmas 2006 is almost upon us! I'm not ready—I'm too young for all of this—stop the world, I want to get off!
2006: Peering back through the mists of time
Well, things have been jolly exciting in 2006. First of all, there have been a flurry of new FPGA device families. In the case of the 65 nm technology node, for example, the folks at Xilinx set the ball rolling with their Virtex-5 offerings, and the guys and gals at Altera quickly responded with their Stratix III devices. Both of these FPGA families boast incredible amounts of logic, memory, DSP, general-purpose I/O (GPIO), and high-speed serial interconnect resources.
Of course, it wasn't just the "big guys" who were enticing us with new offerings - just about everybody in "Programmable Logic Space" had something cool to talk about. For example, those little scamps at QuickLogic started shipping their low-power PolarPro FPGAs that they announced in November 2005; the little rascals at Actel introduced an ARM7-enabled version of their Fusion mixed-signal FPGA family; and the little rapscallions at Lattice Semiconductor regaled us with a positive plethora of announcements, such as the availability of PCI Express IP cores for their LatticeECP2M and LatticeSCM FPGA.
Meanwhile, those little ragamuffins (you thought I'd run out of words, didn't you?) at Synplicity delighted us throughout the year with a barrage of announcements with regard to their ASIC, FPGA, and DSP synthesis offerings. Cool as these announcements were, however, I was particularly interested in Synplicity's proposal for an Open IP Encryption Flow.
2007: Polishing our crystal balls
Predicting the future is always tricky, but I think it's safe to say that 2007 will be much the same as 2006 . . . only different! For example, I think it's safe to say that FPGAs will continue to grow their presence in the non-traditional consumer, automotive, industrial, and mil/aerospace arenas. I also think we can anticipate ongoing developments and announcements in all of the usual "FPGA descriptors" (bigger, better, faster, lower power, and so forth).
I personally am looking to see some strides forward in Electronic System Level (ESL) design and verification tools. And—due to the shear size of the larger FPGAs—I'm anticipating a significant "push" with regards to tools and flows that facilitate incremental design.
I also expect to see more effective/integrated FPGA-based tools for multi-processor designs (including architectural evaluation, profiling, and debugging); some serious FPGA applications with 5G+ SERDES (PCI Express 2.0); continued emphasis by FPGA manufacturers on lowering the power-per-LUT; and increased use of non-volatile FPGAs in low- to medium-density (less than 20K LUT) FPGA applications compared to SRAM-based devices.
But what are we going to see that will really blow our socks off and make us leap from our seats shouting "YES!"? Well, two things spring to mind. . .
On the device front, you may recall a little company called Achronix. Scientists and engineers at Achronix are working furiously on a new type of FPGA. Earlier this year, their test chips achieved speeds of 2 GHz. These little scamps are based on a standard CMOS technology; their extreme speed comes from the fact that internally they use asynchronous techniques (they also boast synchronous inputs and outputs for convenient interfacing to other components). Amazingly enough, these test chips operated correctly over a temperature range of—196 to +130 degrees C. (In a related article, it was announced that the folks at Synplicity are optimizing their Synplify Pro FPGA synthesis tool to work with the Achronix devices.)
And my absolute "all-singing, all-dancing" prediction for 2007? Well, we all know that FPGAs are often used to prototype ASIC designs. The problem is visibility into the internal signals and memory locations inside the FPGA. Existing techniques such as embedded virtual logic analyzers can be useful, but they also have their own "niggles." Alternatively, multiplexing internal values out onto the general-purpose I/O pins dramatically impacts the performance of the FPGA (in a negative way, of course). So can you imagine an incredibly cunning new technology that would allow you to run your FPGA prototype at full hardware speeds while still providing 100 percent visibility into its internal signals (and also its registers and memory contents)? Trust me, this technology is coming our way, and sooner than you think. (If you want to be among the first to know when this little rapscallion becomes available, sign up for my Programmable Logic DesignLine Newsletter.)
There's so much more to talk about, but that would spoil the fun. The year 2007 is racing towards us as I pen these words, and we'll all soon discover the delectations and delights it has to offer. I for one can't wait . . . I'll see you there!
 Clive "Max" Maxfield is president of TechBites Interactive, a marketing consultancy firm specializing in high technology. Max is the author and co-author of a number of books, including Bebop to the Boolean Boogie (An Unconventional Guide to Electronics), The Design Warrior's Guide to FPGAs (Devices, Tools, and Flows), and How Computers Do Math featuring the pedagogical and phantasmagorical virtual DIY Calculator.
Widely regarded as being an expert in all aspects of computing and electronics (at least by his mother), Max was once referred to as "an industry notable" and a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way. Max can be reached at max@techbites.com.
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