Greg Moretti
Site Editor, EDA DesignLine
TechOnline

EDA trends are determined, for the most part, by the requirements of the semiconductors industry. Semiconductors foundries are facing a dual problem: how to continue to profit from leading edge processes by extracting good margins from those customers while servicing the majority of customers that require cost sensitive manufacturing using older processes. EDA vendors thus face a new challenge: support designers that target the latest process and require highly sophisticated tools and methods while also providing reliable and cheaper tools for those costumers using less advanced techniques.

To properly support the first class of customers, EDA vendors will continue to emphasize design for manufacture (DFM) and design for yield (DFY) technologies as well as continuing their efforts to improve both the quality and the speed of verification. The issue of power management will continue to be a focus of EDA vendors, both from a technology point of view and, equally important, from a standard point of view. Many single tool vendors addressing power need to integrate their tools into the flow of the leading vendors. The absence of a single standard may cause some of them to fail due to the high costs of developing interfaces and support for various flows. Mask making and wafer polishing are two areas that will continue to see technological development in 2007 as EDA as vendor struggle to provide support to implementers aiming to produce a more manufacturing friendly design.

But it is becoming clear that such efforts are not enough. Attention is turning to the ESL market, one that has suffered for a few years by a lack of proper definition. Leading EDA vendors are beginning to realize that providing new hardware description languages (HDL) that are just extension of older HDLs is not enough. What is needed are tools that serve system architects who want to design, not implement. There are strong indications that some traditional EDA companies will enter this market that has been dominated by The Mathworks and National Instruments up to now. For 2007 EDA vendors will continue their efforts to integrate tools like MATLAB/Simulink into the design and verification flow since no other alternative is readily available. Effort to standardize languages like Rosetta and Esterel are ongoing but they will not be concluded during the year. It is noticeable that no leading EDA vendor has announced plans to support either language, in spite of the fact that some major systems houses in Europe have been using Esterel for years.

Almost all CEOs of leading EDA companies are engineers and as such focused on the technical aspects of their industry. They have taken the task to support Moore's Law as their primary mission, regardless of the economic realities. Development costs for a product using the latest (65 nm) process now range from a minimum of $20 million to $50 or even more. Therefore only products that have the opportunity to achieve large volume production, in the order of several million pieces, will be profitable. Only few system houses can target those markets, and thus the number of these customers is shrinking. Cadence has already established a tier system for its products, targeting leading edge users with its most advanced and expensive products, while supporting the rest of the design community with proven and less costly tools. This strategy increases returns on the development of tools while providing the majority of designers with quality support and tools that are "foundry proven". More EDA vendors will have to copy this strategy in order to be profitable and avoid becoming a "boutique" vendor. The same can be said for startups. Until now in order to get founded, EDA startups needed to offer a new, leading edge, solution to state of the art problems. There will be opportunities for companies servicing the largest segment of the market, designers targeting older processes, to offer innovative support to lower costs and decrease development time by exploring different approaches to increase productivity and yields. Example of such areas include test, design optimization, and even product inventory and distribution.