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A year after Intel introduced its 90-nanometer Strata-Flash Cellular Memory (M18) family, it's releasing the next-generation device, a 65-nm, 1-Gbit monolithic NOR flash. The latest device replaces its 90-nm predecessor as the most advanced NOR flash in the market. The device further distances Intel from its closest competitor, Spansion, which is moving toward 90-nm production.
The device we evaluated at Semiconductor Insights — part number PF48F6000M0Y0BE — operates on a 1.8-volt power supply and has a die size of 53.5mm2. As with Intel's other StrataFlash, the 65-nm NOR's multilevel cell (MLC) scheme stores two bits in one cell, effectively doubling density. It's targeted at the mobile embedded flash market. NAND flash is knocking at the door and many NAND pundits are optimistic that NAND flash will penetrate deeply into mobile handsets. The 1-Gbit device offers cell phone makers significant storage and execute-in-place capacity in one device. That will make it tougher for NAND flash to penetrate most mobile handsets.
Intel's move to 65 nm
The most notable aspect of Intel's 65-nm NOR flash is its release only a year after the 90-nm device. This is a rapid acceleration for Intel, which typically introduced a new StrataFlash every two to two-and-a-half years. The year's difference is in stark contrast to the 90-nm introduction, which was anticipated long before a device actually hit the market. Intel's move to 90 nm was tougher because the product was significantly redesigned, with a new, more-robust sensing architecture, allowing Intel to scale designs faster. The sensing scheme is more immune to temperature fluctuation and is not affected by variations in reference current, according to technical papers at last year's International Solid-State Circuits Conference.
The 65-nm release proves the redesign at 90 nm, specifically on the sensing scheme, is yielding benefits already. Because Intel could keep the same architecture going from 90 to 65 nm, the devices are drop-in-compatible, easing transitions for cellular OEMs.
The quick shift to 65 nm is also notable competitively. When Intel announced 90-nm flash, Spansion was closing in quickly and had a 110-nm wireless flash comparable to Intel's 130-nm device. Spansion had moved quickly from 230 to 110-nm MirrorBit and was poised to further close the gap if it could transition to 90 nm. A year later, Intel has pushed its flash technology, both in NOR and NAND, and is now at 65 nm, increasing its technology lead a full process generation and gaining a competitive advantage in the mobile market.
Intel's 65-nm device
The 65-nm 1-Gbit NOR flash is made with the tenth generation of the Etox process. The device is fabricated with three levels of copper metallization — two poly levels in CMOS — using dual shallow-trench isolation, triple gate oxides, L-shaped nitride sidewall spacers and cobalt salicide for transistor gates and wordlines. The NOR flash array uses self-aligned floating gates, unloaded bitline contacts, and trench isolation made shallower than the periphery trench. The flash cell measures 0.30 x 0.15 µm for a total area of 0.045 µm2.
Similar to the 90-nm StrataFlash, copper metallization and low-k dielectrics (fluorinated silicate glass, or FSG) provide the backbone of the control circuitry of the device. This is the second Intel device to use copper metallization and, though it is no longer the only memory maker to implement copper (Micron now uses it in some DRAM processes) it is the only one using copper at 65 nm. Copper gives memory designers more flexibility to route longer signal lines.
Similarities abound
Scaling aside, many features are similar with the 90-nm generation of Intel's wireless flash. The basic structure of the memory cell structure is unchanged while scaling occurred in the bitline pitch, wordline pitch and in the physical transistor gate length. The flash cell in the 90-nm device is 0.076 µm2 while the 65-nm cell is 0.045 µm2, a 41 percent decrease. The area factor at 65 nm is 10.65F2, slightly larger than the 9.45F2 area factor for the 90-nm device. That means the cell is relatively larger on the 65-nm device but it's still below the 11 to 14F2 predicted by the Inter-national Technology Roadmap for Semiconductors at these geometries.
At 53.5 mm2, the 65-nm die departs from a recent trend of Intel flash devices doubling the density of the previous generation but with a smaller die. The 90-nm device's die was 43.8 mm2 so moving to 65 nm doubled density — but also increased the silicon area by 22 percent.
The layouts of both dice are similar, with the control circuitry, voltage pumps and some address and data circuitry in a strip at the bottom of the die. The array area is divided into two banks separated by a vertical strip of sense amplifiers and reference cell circuitry. Pads can be found at the top and bottom of both memories. Intel likely increased the size of its array both horizontally and vertically based on the similarities between both devices. That means additional parasitic loading of global bitlines and wordlines did not affect overall device performance. This scaling could have been enabled by using the copper metallization.
The 65-nm die also has a good efficiency rating, which is the ratio of the area occupied by the memory cells vs. the total die area. The simple die efficiency is 45 percent. But after accounting for MLC technology, then the die efficiency rises to 90 percent. This is still superior to Spansion's die efficiency of 35/70 percent on 110 nm, which is just slightly lower than the die efficiency rating on the 90-nm StrataFlash.
While the die efficiency is not as good as the 90-nm device, the effective storage/mm2 per millimeter-squared rating is the highest that Semiconductor Insights has seen in NOR flash.
Geoffrey MacGillivray (geoffrey@semiconductor.com), technology manager for memory at Semiconductor Insights Inc. (www.semiconductor.com).
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