Die size has a direct effect on the manufacturing costs for NAND flash devices. Calculations show that IMFT can manufacture 160 more gross die per wafer, or 34 percent more die per wafer, than the 65-nm device. These advantages will be sure to lower the company's cost structure.
The IMFT 50-nm offering is a SLC device and offers a higher degree of reliability than MLC technology, despite the lower cost of MLCs. Currently all of the 4-Gbit MLC devices that SI has examined are manufactured in the 90-nm node, and it's believed that manufacturers are transitioning the technology to the 65- and 70-nm process nodes. Even as MLC devices transition to those geometries, they will likely have comparable die sizes to IMFT's part.
IMFT is likely to face significant pressure from the other NAND flash players as they move quickly to equalize any competitive advantage that IMFT now holds. Samsung's historical strategy has been to move quickly to new geometries, and it will not sit idly by with IMFT now at the 50-nm node.
A different ballgame
Toshiba, on the other hand, represents a different type of competition. It traditionally uses MLC technology to optimize densities. Even with its 50-nm technology, IMFT still does not match Toshiba's 56.5-Mbit/mm2 rating on its 8-Gbit, 70-nm MLC device.
Toshiba's ability to utilize MLC technology currently gives it an advantage over its competitors. Samsung is moving toward the MLC strategy as well and plans to introduce MLC devices ahead of SLC devices in future generations. Other manufacturers, including IMFT, are stepping up their MLC efforts.
While all manufacturers now have MLC devices, Toshiba is the only one with 70-nm MLC technology that SI has examined. Therefore, expect more MLC devices at advanced geometries in the near future from IMFT and its competitors.
The upcoming arrival of Intel's Robson technology and the implementation of SLC technology will affect the NAND flash landscape as well. Demonstrations of Robson, solid-state drive and hybrid hard-drive technology at the recent Flash Memory Summit show that the technology offers significant advantages over existing architectures. Reliability concerns over MLC NAND flash likely mean that the initial NAND flash devices used in either the Robson or hybrid drive technology will be SLC NAND. The IMFT offering is therefore ideally suited to meet these initial requirements: A single 8-Gbit chip can provide 512 Mbytes of NAND flash buffering.
Fully managed NAND flash solutions also could affect the use of NAND flash, since they will combine wear leveling, ECC and file management into one solution. This will allow OEMs to integrate NAND flash into embedded systems--a task that is difficult with raw NAND flash. Micron's Managed NAND, Sandisk's iNAND and M-Systems' mDOC H3 solutions offer managed solutions, and this gives an advantage to any manufacturer with expertise in flash management. Full control of flash management will also allow those manufactures to compensate for any weaknesses they may have in technology, especially with MLC devices. Therefore, if those interfaces gain market acceptance, demand for MLCflash will increase.
Regardless of where the flash market will go, IMFT is now extremely well-positioned because it has successfully moved its flash technology to the 50-nm node.
In the process of moving ahead, the company addressed several scaling challenges, including cell alignment, tunnel oxide thickness and flash cell coupling. With a 50-nm offering that has put the company on par with the leaders in NAND flash, it can now turn its attention to sub-50-nm technology nodes and MLC technology development.
Now that IMFT has addressed those issues at the 50-nm node, SI expects the company to expand its product line with an MLC device and focus on further process advancement. Indeed, IMFT will need to develop an MLC product in order to compete with other MLC devices for design slots in cost-sensitive applications.
IM Flash Technologies now has a process advantage in the NAND flash market that it will need to continue to aggressively investigate and implement in order to retain its process leadership.
By Geoff MacGillivray (Geoffrey@semiconductor
.com), lead technology analyst for memory at Semiconductor Insights (Kanata, Ontario)
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