The release of a 50-nm IMFT NAND flash signals that NAND flash development at the joint venture will not strictly follow the strategies traditionally used by either of its parents. The most notable change resides with Micron, as its strategy changes from an effective cost innovator to a front-running innovator. Both Intel and Micron's innovative efforts will now be focused on driving their NAND technology into advanced process nodes.
The NAND flash market is a very competitive environment, with all of the major players moving aggressively to new process nodes. By moving quickly to advanced process technologies, IMFT will be able to manufacture its devices with smaller die sizes. The small die sizes translate into more dies per wafer and, thus, lower manufacturing costs, ultimately allowing more price flexibility.
If it is able to maintain this technology leadership, this strategy will give IM Flash Technologies a competitive advantage in the memory industry.
In addition to the advantages provided by moving quickly to advanced process nodes, IMFT may also be able to dynamically adjust fab capacity between NAND and DRAM devices to meet demand. Some NAND flash manufacturers, like Samsung and Hynix, can adjust capacity as well, but Toshiba does not have a significant presence in the DRAM market and does not share that advantage. Toshiba mitigates this disadvantage, however, by offering foundry services to other organizations.
The MT29F4G08AABWP/JS29F04G08 AANC is a 4-Gbit SLC NAND flash manufactured in a three-metal, triple-poly 50-nm CMOS process. It is the most advanced device currently available in the flash market and marks a significant leap forward for IMFT. In moving to the 50-nm node, the company addressed technology and manufacturing issues associated with NAND manufacturing at advanced geometries.
Inside the 4-Gbit SLC
The 4-Gbit device measures 8 x 12.2 mm for a total die area of approximately 98 mm2. In comparison with Micron's 90-nm 2-Gbit device, this represents a 34.7 percent reduction in die size, while the density is doubled. The device's layout is similar to other 4-Gbit parts. The memory arrays are placed in the top portion of the device, and control and peripheral circuitry is found on the bottom of the die. This appears to be the standard design format for the 4-Gbit generation.
The single-transistor NAND flash cell measures 100 x 100 nm for a total area of 0.01 µm2. The technology generation is 50 nm, as determined by the poly 2 world line half-pitch in the memory array. Minimum gate length in the array is 55 nm at the bottom of poly 1 floating gate. The cell size is in line with NAND flash 4F2 cell sizes. The 4F2 cell factor for NAND flash is the smallest cell factor of any memory technology and is the main reason NAND devices have such a low cost-per-bit rating. The effective cell size for the device is 0.0138 µm2. The cell size for the device demonstrates a significant advantage over any other flash memories seen to date and allows IMFT to achieve a very effective die size. IMFT also implemented some novel techniques in cell and contact spacing that SI has not observed in any other NAND flash. These techniques likely assisted lithography tools and enhanced reliability.
The 50-nm process uses dual shallow-trench isolation (STI) triple-gate oxide, along with oxide sidewall spacers. The STI configuration in the array is unique and consists of different isolation dimensions. SI believes that the novel configuration was implemented to reduce local stresses and decrease leakage currents. Other array innovations include a novel source line structure while the metal levels on the device are a combination of tungsten and aluminum.
The device uses SLC technology or stores only one bit per memory cell. SLC technology has been the standard flash technology for many years and is easier to implement than MLC technologies. SLC technology is more reliable than MLC devices and requires less testing time, but suffers a cost disadvantage compared with MLC implementations. Because IMFT was pushing processing limits when it jumped to the 50-nm node, SLC was a better option, since it simplified the transition as much as possible.
The 4-Gbit generation
IMFT's newest device now has the smallest die size and thus the lowest cost of any of the 4-Gbit parts examined by SI to date. Since 55- or 50-nm process geometries were not anticipated to hit the market until late 2006 or early 2007, IMFT's device represents a significant accomplishment. As it moves ahead of NAND incumbents Toshiba and Samsung in process technology, it is changing the competitive landscape in that market segment.
The 4-Gbit NAND flash generation is becoming an extremely competitive area, with several vendors offering similar devices. The IMFT device is 25 percent smaller than the next smallest 4-Gbit offering from Samsung, which is manufactured at the 65-nm node--the second most-advanced process currently available.
