Samsung has established the No. 1 market position in the top two semiconductor memory markets. But even as the memory leader, the company is not known for coasting. It continues to scale memory products aggressively into advanced geometries, a technique it used to achieve its current position. The latest example of Samsung's scaling efforts is the 4-Gbit NAND flash, the first standalone memory to be manufactured at the 65-nanometer node. The device has the small- est 4-Gbit die size seen by Semiconductor Insights to date. That gives Samsung a cost advantage in the NAND market.
Samsung holds the top position in both the NAND market (52.9 percent) and DRAM sector (32.1 percent), the two largest memory markets. In fact, Samsung is more than twice as large as its nearest competitor in NAND and nearly twice as large as the second-place manufacturer in the DRAM space. The NOR market is the only major memory segment in which Samsung does not hold the top spot; it was the fourth-ranked NOR manufacturer in 2005, according to iSuppli Corp.
The secret to Samsung's success is its aggressive strategy of moving its products into advanced process technologies as rapidly as possible. By moving quickly to advanced process technologies, Samsung is able to manufacture devices with smaller die sizes. Those small die sizes translate into more dice per wafer and, thus, lower manufacturing costs--and ultimately, more price flexibility. The strategy has given Samsung a competitive advantage in the memory industry that other manufacturers have been unable to duplicate.
Recent examples of Samsung's technology scaling include the first 90-nm DRAM, a device that was manufactured several months ahead of any other 90-nm DRAM. Samsung will also likely be the first manufacturer to produce 80-nm DRAMs and will be doing so while many competitors are still ramping volume in their 90-nm process technologies. It is now very clear that NAND flash production will take place on much more advanced process nodes than DRAM. In the NAND market, Samsung was the first manufacturer to the 70/73-nm node and is now the first to the 65-nm node. NAND competitors like Toshiba and Hynix are close behind, however, and have some technological advantages that help their position.
The Samsung 65-nm 4-Gbit NAND flash (K9F4G08U0A) is a monolithic device that uses single-bit-per-cell technology. The device is fabricated using a triple-metal, double-poly, 65-nm CMOS process on a 131-mm2 die. The single-transistor flash cell measures approximately 0.126 x 0.13 micron, for a total cell area of only 0.016 micron2. The overall bit-efficiency rating is 31.3 Mbits/mm2.
The 65-nm device is 15.9 percent smaller than the previous 4-Gbit-generation device, which was manufactured with 73-nm process geometry. However, the die efficiency on the 65-nm device is 54 percent, down approximately 6 percent from the 73-nm device. The loss in die efficiency is likely due to scaling differentials between the array and peripheral circuitry.
The 65-nm and 73-nm devices share several innovative process technologies that have been successfully scaled from 73-nm geometries to 65 nm. These features include a self-aligned floating-gate poly cell along with similar control-gate and floating-gate structures. However, the 65-nm device includes some new process techniques to deal with floating-gate coupling, select transistor contacts and shallow trench-isolation depths.
The device uses single-bit-per-cell (SBC) technology, storing only 1 bit per memory cell. SBC technology has been the standard flash technology for many years and is easier to implement than multilevel-cell (MLC) technologies. SBC technology is more reliable than MLC and requires less testing time. But it suffers some cost disadvantages compared with MLC implementations because of the lower density.
The 4-Gbit NAND flash generation is becoming an extremely competitive area, with several vendors offering very similar devices. The Samsung K9F4G08U0A has the smallest 4-Gbit die size that Semiconductor Insights has observed to date. It is 5 percent smaller than the next smallest 4-Gbit device, an offering from Toshiba that is manufactured at the 90-nm node. Samsung's early 4-Gbit offerings were not as competitive as Toshiba's 4-Gbit, 90-nm MLC device, and it is likely that this part was expressly designed to compete with Toshiba's offering.
The die size advantage offered by Samsung's 65-nm technology allows the company to manufacture approximately 469 gross dice per 300-mm wafer. This is 6.4 percent more than the Toshiba 4-Gbit offering and 11.4 percent more than Hynix/ STMicroelectronics' 70-nm product.
