|
|
On-Demand Webinars |
|
| Sort by Company |
|
|
|
|
|
|
|
Event |
|
Date/Time |
|
Length |
| |
Revolutionized Advanced DRC Checks and LVS Debug
Mentor Graphics |
|
Nov 04, 2008 |
|
30 min. |
| |
Mentor Graphics' Place and Route Solution
Mentor Graphics |
|
Nov 04, 2008 |
|
15 min. |
| |
Buying Time: Using Signal Integrity and Common Sense to Meet Timing Margins for High Speed Memory Interfaces
Synopsys |
|
Oct 15, 2008 |
|
60 min. |
| |
Decoding the Real Low Power Benefits of DDR for Embedded Applications
Synopsys |
|
Oct 01, 2008 |
|
60 min. |
| |
Avoiding the Landmines When Using a DDR Interface on your Next SoC
Synopsys |
|
Sep 16, 2008 |
|
60 min. |
| |
Advanced DFM and AAA — Mentor and TSMC Collaborate for Success
Mentor Graphics |
|
Aug 07, 2008 |
|
60 min. |
| |
Executive Presentation: Meeting the Critical Challenges of IC Implementation
Mentor Graphics |
|
Aug 07, 2008 |
|
60 min. |
| |
Achieving Optimal Performance and Low Power for SATA Device Designs
Synopsys |
|
Jul 31, 2008 |
|
60 min. |
| |
Building a VMM-Based Constrained Random Environment for Bus Protocol Verification
Synopsys |
|
Jul 15, 2008 |
|
60 min. |
| |
Co-simulation Enables Efficient Co-Design of WLAN Antenna and Circuitry
Agilent Technologies |
|
May 28, 2008 |
|
60 min. |
| |
Using the New SystemC TLM-2.0 Standard for the Creation of Virtual Platforms for Software Development and Architecture Design
CoWare |
|
May 20, 2008 |
|
60 min. |
| |
Chip-Package Co-Design: Applying Chip Power Model in System Power Integrity Analysis
Apache Design Solutions |
|
May 08, 2008 |
|
60 min. |
| |
Selecting the Optimal Embedded Memory IP Architecture
Synopsys |
|
May 01, 2008 |
|
60 min. |
| |
DSPF Back-Annotation Flow in Design Architect IC
Mentor Graphics |
|
Feb 06, 2008 |
|
15 min. |
| |
Approaching Yield in the Nanometer Age
Mentor Graphics |
|
Feb 06, 2008 |
|
90 min. |
|
|
| MORE ON-DEMAND WEBINARS |
|
|
|
|
10AM PT / 1PM ET / 6PM GMT 