Overview:
As FPGA devices become denser and faster, they become the target of complex designs and applications that traditionally belonged in an ASIC. This trend is stressing the limits of traditional FPGA timing analysis tools, affecting designer productivity. FPGA designers have started to adopt more ASIC style timing analysis tools to meet their timing closure needs. During this net seminar, Altera will demonstrate how native Synopsys Design Constraints (SDC) support can help FPGA designers close timing. In addition, the net seminar will provide an overview of the TimeQuest timing analyzer, a new, next-generation ASIC-strength timing analyzer with native support for the industry-standard SDC format.
The net seminar describes how to:
- Address the growing difficulties of complex clocking schemes (source synchronous, multi-plexed clocks) in FPGA designs
- Understand the SDC format to better constrain complex designs
- Learn how the TimeQuest timing analyzer can help designers create, manage, and analyze complex timing constraints, and to quickly perform advanced timing verification.
Who Should Attend:
- Engineers designing FPGAs with complex clocking schemes (source synchronous etc.)
- ASIC engineers starting an FPGA or structured ASIC design
- Engineering and technical managers
Drawing:
All participants who attend this net seminar live and complete the post-presentation survey will be entered into a drawing for a chance to win an Epson P2000 Multimedia Viewer (US$500.00).
Official Rules
PRESENTERS
Jordon Inkeles
Senior Manager, Software Marketing
As Sr. Manager of Software Marketing, Jordon Inkeles is responsible for driving Altera's industry-leading FPGA, CPLD, and structured ASIC design environment: Quartus® II design software. Inkeles joined Altera in June 1999. During his tenure at Altera, he has held several marketing positions in the component, online, corporate, and software marketing organizations. Before joining Altera, he held marketing and engineering positions at Semtech and Xicor, Inc. Inkeles holds an Electrical Engineering degree from UC Santa Barbara and an MBA from Tulane University.
Alessandro Fasan
Senior Manager, Software Technical Marketing
Alessandro Fasan joined Altera in November 2005 where he leads the technical marketing team for Altera's Quartus II design software. Prior to joining Altera, Fasan worked at Synopsys as product marketing manager for their Magellan product, technical marketing manager for their flagship VCS simulator, and field engineer supporting VCS and Vera. Prior to Synopsys, Fasan spent seven years as an IC design and verification engineer with ST Microelectronics working on MPEG2, microprocessor (x86), and memory controller designs. Fasan holds a "Laurea in Ingegneria Elettronica" (MSEE) from the University of Padova, Italy and is an MBA candidate at San Jose State University. Fasan was awarded two US patents.
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