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Overview:
Designs targeting today's advanced devices, such as Xilinx Virtex-4 FPGAs, incorporate a wide range of challenges including unpredictable routing results, routing congestion, tightly packed designs, heavily constrained interconnect, clock complexity, paths-spanning hierarchy, and inconsistent performance levels.
PlanAhead delivers a unique solution by filling the gap between synthesis and place-and-route using techniques commonly used by ASIC designers. The result is a significant reduction in both the number and the length of design iterations. This Tech-Online Webcast will use several Virtex-4 design examples to highlight the unique features of the PlanAhead Design and Analysis Tool. It is intended to provide attendees with answers to questions such as “How can I …”
- Create a PlanAhead Project?
- Visualize the interconnect and data flow of my design?
- Analyze, identify and constrain critical logic for implementation?
- Configure, monitor and manage multiple ISE runs?
- Improve timing by examining previous ISE results?
And much more.
This Webcast will demonstrate how PlanAhead, combined with the ISE 8.1i Design Tools, can deliver:
- An average of 30% faster performance compared with competing solutions, for designs targeting both Spartan and Virtex FPGAs
- Over 56% faster performance for more complex designs
- 50% shorter design time with better design results
- An unparalleled environment for IP reuse and team-based design
Webcast Attendees Will Learn:
- How to achieve maximum performance for their Virtex-4 designs
- How to shorten their overall design time
- How to use PlanAhead to leverage results through IP creation and reuse.
Who Should Attend:
- High-density FPGA engineers
- Designers of complex, high-performance systems
- System Architects
- Engineering or technical managers
Presented by:
Mark Goosman
Product Marketing Manager, Xilinx. Inc.
Mark Goosman is product marketing manager for the Product Solutions Marketing group at Xilinx. In this role, Goosman is responsible for outbound marketing the Xilinx ISE Design Tools, including the PlanAhead™ Design and Analysis Tool. Goosman joined Xilinx in 1996 and brings over 20 years of experience in the technical software industry where he served in a variety of marketing and sales roles including technical sales, product definition, software development, and technical marketing. Prior to Xilinx, Goosman held various positions at Research Systems, Visual Numerics and Precision Visuals. Goosman holds a bachelor's degree in computer science from Colorado State University.
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