Overview:
As designers strive to achieve higher performance while meeting critical timing margins, one consistently vexing performance bottleneck is the memory interface. Today's Virtex™-4 FPGAs provide embedded blocks, called ChipSync™ in every I/O that make the interface design easier and more reliable.
Yet designers must create, verify, and implement the interface and controllers tied to the rest of the design.
But, what if these difficult tasks were taken care of by the FPGA vendor? What if a designer could simply use a GUI to input the memory system parameters and generate RTL code without writing it from scratch? Finally, what if the interface is based on hardware verified designs? All this is now possible using Xilinx Memory Interface Generator (MIG). This seminar will discuss the memory interface controller design challenges and how to use the Virtex-4 FPGAs and the MIG to build a complete memory interface solution for your own application. This informative webcast is brought to you by Xilinx and Avnet.
Webcast Attendees Will Learn:
- Learn how to successfully address your design challenges using Virtex-4 FPGAs
- Build highest bandwidth memory interfaces, like 667 Mbps DDR2 SDRAM, with unmatched reliability.
- Accelerate your design cycle using the latest software tools from Xilinx
Who should Attend:
- ASIC and FPGA engineers
- System architects
- Engineering or technical managers
Speaker Bios:
Adrian Cosoroaba
Marketing Manager, Virtex Solutions, Xilinx, Inc.
Adrian is responsible for worldwide marketing activities related to Memory Solutions. He brings to Xilinx over 19 years of semiconductor experience in memory applications and marketing. Prior to joining Xilinx, he held a range of applications engineering and strategic marketing positions at Fujitsu and helped define through JEDEC the DDR SDRAM and SSTL I/O standards. He holds an M.S. in Electrical Engineering from Ohio State University and a B.S. in Engineering Physics from University of California at Berkeley. 
Maria George
Senior Applications Engineer, Xilinx, Inc
Maria holds a Master of Science degree in Electrical Engineering from Santa Clara University with an emphasis in hardware design. With Xilinx since 1999, Maria develops HDL reference designs and application notes for memory interfaces in her capacity as a Senior Applications Engineer in the Advanced Product Division.
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