Overview
Signal integrity has become a critical issue in the design of high-speed systems. The amount of available timing margin is shrinking proportionately with increasing performance requirements. In addition, there is significant pressure to keep system costs down by reducing the board area and by minimizing the number of board layers. All these factors make signal integrity a challenge in high-speed systems. If not managed properly, signal integrity can cost companies millions of dollars due to increased engineering costs, delayed products, missed market opportunities, and lost revenues. Selecting the right FPGA that meets specific signal integrity requirements is critical for individual design success. Attend the net seminar and learn to:
- Perform a thorough signal integrity assessment and understand the various factors that need to be taken into consideration
- Evaluate the right FPGA for your high-speed system
- Build reliable high-speed interfaces with good timing margin and excellent signal quality
- Maximize interface performance by optimizing signal integrity in your system
Who Should Attend
- Hardware Engineers and Managers
- Board Designers
- Signal Integrity Engineers
- System Architects
Drawing
All participants who attend the net seminar live and complete the post-presentation survey will be entered into the drawing for a chance to win a Gateway DVD Player/Recorder (US$250 value) , built with Altera® devices. Official Rules
Presenters
Lalitha Oruganti
I/O and Signal Integrity Specialist at the Altera Corporation
Since joining Altera Corporation seven years ago, Lalitha Oruganti has held multiple roles in product engineering, product analysis and technical marketing. Her experience with Altera devices spans from the MAX® family of products through the latest Stratix II FPGA offerings. She is currently focused on marketing Altera's I/O and Signal Integrity solutions. Oruganti holds a Masters degree in Electrical Engineering from Florida State University. 
Vipul Badoni
Vipul Badoni has been with Altera since March, 2002 where he heads up the High-Speed I/O Applications Engineering Group. Prior to Altera he was director of optical engineering at Nayna Networks where he led the development of optical components for an all optical cross-connect switch. Before that he was at LSI Logic as manager for applications engineering for the GigaBlaze (High-Speed Serializer-Deserializer) Core. Mr. Badoni started his career at Fujikura as a communications scientist, designing, testing and manufacturing components for high-speed optical link modules. Mr. Badoni has a Bachelors in Electronics and Communication Engineering from Delhi Institute of Technology, New Delhi,India; and MSEE from University of North Carolina at Charlotte with a concentration in Free Space Optics. He also has to his credit courses in the field of Optical Communications from Stanford University.
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