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Overview
The transition from parallel to serial interconnect is happening at a rapid pace to address the ever-increasing bandwidth requirements of today's applications. The number of serial protocol standards has increased in recent years as more and more designers adopt serial interconnect technology. Designers are looking to FPGA suppliers for the answer. Designers want integrated high-speed serial transceivers that support the widest range of protocol standards while maintaining low power and optimal signal integrity. They also want not just the FPGA device but the complete protocol solution including intellectual property (IP), reference designs, development boards, and tools to simplify their design.
This net seminar will help you understand the solutions available for your next serial protocol design. At the net seminar, you'll learn:
- Serial interconnect technology trends
- How pre-emphasis and equalization improve signal integrity
- How hard IP blocks integrated into the Stratix® II GX device simplify designing to PCI Express, XAUI, Gigabit Ethernet, CEI-6G, SerialLite II, serial digital interface (SDI), SONET, and Serial RapidIO™ (SRIO) protocols
- What to expect from chip vendors to simplify transceiver design and reduce time-to-market.
Who Should Attend
- System architects
- High-speed system design engineers
- Backplane design engineers
- Signal integrity engineers/designers
- FPGA designers
Drawing
All participants who attend this net seminar live and complete the post-presentation survey will be entered into a prize drawing for a chance to win an RCA Lyra Audio/Video 20 GB Jukebox (US $400.00 value), built with Altera® devices. Official Rules
Presenters
Joel Martinez
Product Marketing Manager, High-Density FPGA Products
Joel Martinez is Altera Corporation's product marketing manager for the Stratix GX series of FPGAs with high-speed transceivers. Joel joined Altera in 2002 and has more than 17 years of experience in semiconductors. Joel has held engineering and marketing positions at Agere Systems, Hitachi, Sony, TriQuint, and National Semiconductor. He holds a BSE from San Francisco State University. 
Venkat Yadavalli
Member of Technical Staff, High-Speed Applications group
Venkat Yadavalli has been with Altera since 2003 where he is part of the High-Speed Applications group. Prior to Altera he was at LSI Logic in the High-Speed ASIC I/O group. He has worked on architecting, designing and testing the designs and devices that involved GigaBlaze (high-speed serializer/deserializer (SERDES)) cores and HyperPhy (source synchronous) cores. Venkat has a bachelors degree in electronics and communication engineering from Osmania University, Hyderabad, India and a masters degree in electrical engineering from University of Louisiana, Lafayette with concentration in telecommunications.
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