In order to continually decrease costs and increase performance in today's highly competitive computing, consumer electronics and communications markets, it is highly advantageous to reduce the integration time and risk in developing next generation systems-on-chip (SoC's). Some of the factors that adversely impact growth in these markets are related to increasing mask costs especially at the 90 nm nodes and below, longer development and verification cycle times and, especially in consumer electronics, shorter product windows. Third party semiconductor intellectual property (IP) industry has emerged to meet this demand.

This webinar focuses on the challenges, and solutions, of one of the significant growth areas for third party IP namely high speed serial interconnects such as PCI Express, SATA and XAUI. At operating speeds of 2.5 Gb/s and higher on a standard printed circuit board, many challenges arise, for example isolating manufacturing defects such as transmission line loss, impedance discontinuities and crosstalk. But these are just some of the challenges. Others include verification, chip integration of third party IP, built-in test capabilities, ESD, yield across manufacturing variations, meeting overall jitter/power budgets and bit error rate specifications. And finally, production testing of high speed serial interconnects is very difficult and a solution to this problem using on-chip ATE will be presented.

For most SoC designers the value of their IP is in the middle of the chip and the desired result of purchasing any high speed serial interconnect IP is simple, it should just work. This webinar will describe the challenges and what to look for when selecting an IP Vendor for PCI Express, SATA and XAUI.