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Overview:
Controlling jitter is essential for successful design of high-speed of systems. In our third web seminar on signal integrity, Dr Howard Johnson explains the fundamentals of jitter in the context of a timing budget.
Jitter has many causes, including crosstalk, clocking schemes, and reflections in the data path. Left uncontrolled, jitter can eat into the timing margin of your high-speed interfaces, causing unreliable data capture, or even system failure. You will learn:
- Fundamentals of jitter: causes and effects of intrinsic jitter, input clock quality, and the effects of noise on FPGA clock generation circuitry
- Some basic design practices to control jitter and build robust interfaces
- How innovative Virtex-4 technology manages jitter at the chip level and simplifies system design
Who Should Attend
- ASIC and FPGA engineers
- Designers of complex, high-performance systems
- System architects
- Engineering or technical managers
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The newest version of Virtex FPGAs from Xilinx provide a boost in speed, reduction in power, and significant reduction in cost that promises to propel many new designs.
Jim Harrison
West Coast editor for Electronic Products Magazine |
Presented by:
Dr. Howard Johnson
One of the foremost authorities on Signal Integrity, with over thirty years of experience in the field, Dr Howard Johnson is the author of "High-Speed Digital Design: A Handbook of Black Magic", considered to be a must-read for all engineers building a high-speed system.
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