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Overview:
A typical FPGA design flow follows the design and debugging through HDL synthesis, functional simulation, FPGA place and route, timing simulation, and hardware debugging. Hardware debugging typically involves hardware: probes, scopes and logic analyzers. But with new debugging tools, such as Lattice's ispTRACY, hardware debugging can be done easily, in real-time through software. High-performance FPGA validation becomes fast and easy. Attend this webcast and learn how to:
- Fit the ispTRACY logic analyzer into the FPGA design flow
- Implement ispTRACY as part of a system design
- Observe internal node states while the device is running in-system at system speed
- Perform easy, real-time, high-performance FPGA validation
Drawing
- 1 participant who attends the live broadcast and fills out the feedback form will receive an ispLEVER
Development Tool for Lattice FPGA and CPLD design.
Official Rules
Presented by:
Rich Hoge, Applications Engineer Lattice Semiconductor
Rich Hoge is an Applications Engineer at Lattice Semiconductor
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