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Overview:
System power consumption affects cost, reliability, and performance. Today's Platform FPGAs provide programmable SoC capabilities making accurate power analysis a key requirement.
Xilinx designed the Virtex-4 Multi-Platform FPGA family with key power-saving technologies such as triple-oxide technology for static power reduction and programmable embedded IP for dynamic power reduction saving 1 to 5 Watts compared to competing FPGAs. Static power is pre-determined by the FPGA vendor and even our competitors confirm our lowest static power in the industry. In addition power saving technologies used to build the FPGA, users' design decisions and operating conditions impact total power.
In this webcast, system architects will learn how to make accurate total power estimates based on their estimated resource utilization, toggle rates (switching activity), clock frequency, embedded IP configurations, and operating environment. FPGA designers will learn how to use XPower tools to perform accurate comprehensive power analysis using actual implementation data. Webcast Attendees Will Learn:
- Power analysis tools and methodologies for system architects and FPGA design engineers
- How to use Xilinx® web power tools for power estimation at architecture level before the design is implemented in the FPGA
- How to use XPower tools for detailed power analysis after design is implemented using toggle rates, clock frequencies, and exact resource utilization
- How the tools correlate with actual hardware
- How to plan and budget for power in their leading edge designs
Who Should Attend:
- ASIC and FPGA engineers
- Designers of complex, high-performance systems
- System architects
- Engineering or technical managers
The newest version of Virtex FPGAs from Xilinx provide a boost in speed, reduction in power, and significant reduction in cost that promises to propel many new designs.
Jim Harrison
West Coast editor for Electronic Products Magazine
Presented by:
Matt Klein
Sr. Staff Engineer, Applications Engineering, Advanced Products Division, Xilinx Inc.
Matt has worked with FPGAs for nearly 20 years, having done close to 50 FPGA designs and worked on the system architecture of several large products before joining Xilinx. Matt served as System Architect and Hardware Technical Lead at Hewlett Packard and Pinnacle Systems, developing products ranging from Digital Synthesizers to Digital Radio Bit Error Rate Testers to Video Servers. Matt holds patents in Digital Radio and Video Systems. He received a B.S.E.E from Case Western Reserve University and an M.S.E.E. from Santa Clara University.
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