Overview:
Designers today have to contend with increasing design complexity while maintaining lower overall system costs. This often means sacrificing features or performance but not any more - Come and learn how to target the smallest & most cost effective FPGA for your next design. Xilinx and Synplicity invite you to attend a free, one hour seminar where you will learn cost reduction techniques by minimizing logic utilization and targeting lower speed-grade devices without sacrificing features and while meeting your required performance.
In this technical seminar you will learn to:
- Use the silicon features that allow you to minimize the FPGA device utilization
- Use the Synplicity synthesis tools to utilize these features and maximize performance
- Apply appropriate synthesis constraints and use timing-driven synthesis for maximum area/cost reduction
Using the techniques elaborated in the seminar you will be able to meet aggressive feature and performance with the lowest possible cost FPGA
Who Should Attend:
Design engineers and design managers seeking to improve their design performance and lower their system costs.
Presented by:
Peter Mar
Sr. Field Applications Engineer at Synplicity
Pete currently works as a Field Applications Engineer for Synplicity. He has a BSEE degree from Northeastern Univeristy and numerous years of experience in the FPGA and ASIC industries. Pete has worked in an applications role at various companies including Summit Design and Compass Design.
Suhel Dhanani
Sr. Marketing Manager for High Volume Products at Xilinx.
Suhel has almost 10 years of marketing experience in the semiconductor industry. He has completed graduate work in Management Science from Stanford and also holds M.S.E.E. and M.B.A. degrees from Arizona State University
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