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On-Demand Webinar |
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| Learn About High-Speed Clocking Architecture and Oscillator Selection for FPGAs |
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Overview:
In high-speed or wide bus interfaces, such as gigabit transceiver or high-speed memory interfaces, room for clock uncertainties and variations is small. Unfortunately, we do not live in an ideal world where clock oscillators have frequency variations and are exposed to jitter. This netseminar covers various clock network topology for FPGAs. It also goes through a detailed discussion on jitter, its components and causes of each. At the end, we will provide guidelines on how to select the right oscillator for your high speed design.
At the net seminar, you'll learn about:
- Synchronous and asynchronous clock network topology
- Components and causes of clock jitter
- How to select the right oscillator for your high-speed designs
Who Should View
- System Architects
- Hardware and system design engineers
- FPGA developers
Drawing
All participants who attend this net seminar from December 12, 2006 to December 27, 2006 and complete the post-presentation survey will be entered into the drawing for a chance to win an Epson P-2000 Multimedia Storage Viewer (US$500)!
Official Rules
Presented by:
Leonard Dieguez
High Speed Design Engineer, High Speed Board Development, Component Applications
Leonard Dieguez joined Altera in September 2005 as a high-speed design engineer working in the component applications' high-speed board development group. Mr. Dieguez has over 15 years of industry experience, including eight years in serial communications. He began his career in serial communications at JNI designing Fibre Channel (host bus adapters) HBAs. He has published papers on novel CDR techniques using sampled delay lines in FPGA fabrics. Mr. Dieguez graduated with his BSEE from the University of South Florida in 1986, with major course work in microwave theory and distributed networks. After graduation, Leonard Dieguez served in the United States Navy as a helicopter pilot and is a veteran of the Gulf war.
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| Altera Corporation www.altera.com is the world's pioneer of system-on-a-programmable-chip (SOPC) solutions. With annual revenues in CY 2005 of $1.12 billion, Altera combines the reprogrammable logic technology originally invented in 1983 with software tools, intellectual property (IP), and design services to provide high-value programmable solutions to approximately 14,000 customers worldwide. Altera is headquartered in San Jose, California, and employs approximately 2,300 people in 14 countries. |
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