Overview:
RFIC / MMIC design does not end when the chip layout is complete. Integration of the IC with the module and package (and even the system board) is a huge challenge, and becoming more difficult with the emergence of multi-chip RF modules, and with stacked-die RF modules on the horizon. When integration problems occur at the end of the design cycle, the time and cost required to address these problems can kill the project. This webcast illustrates how these problems can be minimized with an IC-module-package-board co-design methodology, where RFIC / MMIC integration issues are detected early with the use of nonlinear simulation and 3D EM analysis in an integrated design environment.
Duration: One hour
Who should view this webcast:
Designers of RFICs, MMICs and RF modules
Giveaway:
Registrants who completely fill out the feedback form by October 13, 2009 will be eligible to win one of two $75 Amazon.com gift certificates. Drawing only open to residents of the 50 United States and Canada (except Quebec). Official Rules
Presenter:
Hee-Soo Lee, Agilent Technologies
HeeSoo Lee holds a BSEE degree from the Hankuk Aviation University, Korea. He has more than 20 years of design and simulation experience in the area of RF and MW designs, and currently works for Agilent EEsof as 3D EM solutions technical lead.
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